It is known that reduced surface field (RESURF) techniques can be applied to various semiconductor devices to improve their voltage breakdown and their series ON-resistance. However, simultaneous optimization of series ON-resistance and breakdown voltage BVdss often requires choices of doping and device geometry that may be unduly restrictive and difficult to achieve consistently in volume manufacturing. Accordingly, there is an on-going need for improved RESURF structures and methods that allow greater flexibility in device design and the charge balancing needed for RESURF behavior.
For convenience of explanation, the improvements described herein are illustrated by means of lateral diffused field effect MOS transistors identified by the abbreviation “LDMOS”, but persons of skill in the art will understand that they may be applied to other types of transistors and diodes and are not intended to be limited merely to the exemplary LDMOS transistors. It will be further understood by persons of skill in the art, that the abbreviation “MOS” for “metal-oxide-semiconductor” is not limited merely to field effect structures employing metal gates and oxide insulators, but that any type of conductor may be used for the gates and any type of dielectric for the insulator in such devices.
FIG. 1 is a simplified schematic cross-sectional view of N-channel LDMOS transistor 20, according to the prior art, and FIG. 2 is a simplified plan view of transistor 20. Dimensional arrows are provided in FIG. 2 and other FIGS. to indicate the relative lateral extent of various regions. Transistor 20 comprises substrate 22, P-type body (P BODY) region 24 overlying substrate 22, P+ body contact region 26, N+ source region 28, N-type drift (N DRIFT) region 30 in which is formed N+ drain region 32. Portion 24′ of P BODY region 24 underlies N DRIFT region 30. Dielectric region 34 extending partly under conductive gate 38 is generally placed in N DRIFT region 30 adjacent N+ drain region 32. Gate dielectric 36 separates conductive gate 38 from semiconductor surface 21. P BODY region 24 and source region 28 are often shorted together and external body-source (B/S) terminal 29 is generally provided to body contact region 26 and source region 28. Gate (G) terminal 39 is provided to conductive gate 38. Drain (D) terminal 33 is provided to drain region 32. As noted in FIG. 1, electron current Ids flows between source region 28 and drain region 32, when device 20 is appropriately biased. In order to obtain RESUF action, the charge in N DRFT region 30 and underlying portion 24′ of P BODY region 24 should be approximately balanced. In the prior art, this is usually accomplished by appropriately choosing thickness 25′ and doping of P BODY region 24′ and thicknesses 31, 35 and doping of N DRIFT region 30. Double RESURF action can be provided by having an N-type region, e.g., an N-type buried layer (BL) (not shown) at the interface between P-BODY region 24 and substrate 22.